Interfacing of LPC2148 with UART1 and GSM Module

Uart uses TxD(Transmit) Pin for sending Data and RxD(Receive) Pin to get data. UART sends & receives data in form of chunks or packets.

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Registers used for UART programming in LPC214x

Data Related Registers :

1) U0RBR – Receiver Buffer Register (READ ONLY!): This register contains the top most byte(8-bit data chunk) in the Rx FIFO i.e the oldest received data in FIFO. To properly read data from U0RBR , the DLAB(Divisor Latch Access) bit in U0LCR register must be first set to 0. Also , as per the user manual “The right approach for fetching the valid pair of received byte and its status bits is first to read the content of the U0LSR register, and then to read a byte from the U0RBR.” (Note : If you are using 7,6 or 5 Bits for data then other remaining bits are automatically padded with 0s)

2) U0THR – Transmit Holding Register (WRITE ONLY!): U0THR contains the top most byte in Tx FIFO and in this case its the newest(latest) transmitted data. As in the case with U0RBR , we must set DLAB=0 to access U0THR for write operation.

Baud Rate Setup related registers :

1) U0DLL and U0DLM – Divisor Latch registers: Both of them hold 8-bit values. These register together form a 16-bit divisor value which is used in baud rate generation which we will see in later section. U0DLM holds the upper 8-bits and U0DLL holds the lower 8-bits and the formation is “[U0DLM:U0DLL]“. Since these form a divisor value and division by zero is invalid, the starting value for U0DLL is 0x01 (and not 0x00) i.e the starting value in combined formation is “[0x00:0x01]” i.e 0x0001. Please keep this in mind while doing baud-rate calculations. In order to access and use these registers properly, DLAB bit in U0LCR must be first set to 1.

2) U0FDR – Fractional Divider Register : This register is used to set the prescale value for baud rate generation. The input clock is the peripheral clock and output is the desired clock defined by this register. This register actually holds to different 4-bit values (a divisor and a multiplier) for prescaling which are:

  1. Bit [3 to 0] – DIVADDVAL : This is the prescale divisor value. If this value if 0 then fractional baud rate generator wont have any effect on Uart Baud rate.
  2. Bit [7 to 4] – MULVAL : This is prescale multiplier value. Even if fractional baud rate generator is not used the value in this register must be more than or equal to 1 else UART0 will not operate properly.
  3. Other Bits reserved.

Remark from Usermanual : “If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of the DLL register must be 2 or greater!

Control and Status Registers :

1) U0FCR – FIFO Control Register : Used to control Rx/Tx FIFO operations.

  1. Bit 0 – FIFO Enable : 1 to Enable both Rx and Tx FIFOs and 0 to disable.
  2. Bit 1 – Rx FIFO Reset : Writing a 1 will clear and reset Rx FIFO.
  3. Bit 2 – Tx FIFO Reset : Writing a 1 will clear and reset Tx FIFO.
  4. Bits [7 to 6] : Used to determine that how many UART0 Rx FIFO characters must be written before an interrupt is activated.
    [00] (i.e trigger level 0) for 1 character.
    [01] (i.e trigger level 1) for 4 characters.
    [10] (i.e trigger level 2) for 8 characters.
    [11] (i.e trigger level 3) for 14 characters.
  5. Others bits are reserved.

2) U0LCR – Line Control Register : Used to configure the UART block (i.e the data format used in transmission).

  1. Bit [1 to 0] – Word Length Select : Used to select the length of an individual data chunk. [00] for 5 bit character length. Similarly [01] , [10] , [11] for 6 , 7 , 8 bit character lengths respectively.
  2. Bit 2 – Stop bit select : 0 for using 1 stop bit and 1 for using 2 stop bits.
  3. Bit 3 – Parity Enable : 0 to disabled Partiy generation & checking and 1 to enable it.
  4. Bit [5 to 4] – Parity Select : [00] to Odd-parity , [01] for Even-parity , [10] for forced “1”(Mark) parity and [11] for forced “0”(Space) parity.
  5. Bit 6 – Break Control : 0 to disable break transmission and 1 to enable it. TxD pin will be forced to logic 0 when this bit is 1!
  6. Bit 7 – Divisior Latch Access bit : 0 to disable access to divisor latches and 1 to enable access.

3) U0LSR – Line Status Register : used to read the status of Rx and Tx blocks.

  1. Bit 0 – Receiver Data Ready(RDR) : 0 means U0RBR is empty(i.e Rx FIFO is empty) and 1 means U0RBR contains valid data.
  2. Bit 1 – Overrun Error(OE) : 0 means Overrun hasn’t occured and 1 means Overrun has occured. Overrun is the condition when RSR(Receive Shift Register)[See note 1] has new character assembled but the RBR FIFO is full and the new assembled character is eventually lost since no data is written into FIFO if its full. (Note: Reading U0LSR clears this bit)
  3. Bit 2 – Parity Error(PE) : 0 mean no parity error and 1 mean a parity error has occured. When the value of the parity bit in the recieved character is in wrong state then a parity error occurs. (Note: Reading U0LSR clears this bit)
  4. Bit 3 – Framing Error(FE) : 0 means no framing error has occured and 1 means that a framing error has taken place. Framing error occurs when the stop bit of a received character is zero. (Note: Reading U0LSR clears this bit)
  5. Bit 4 – Break Interrupt : 0 means no Break Interrupt occures and 1 means that it has occured. A Break Interrupt occurs when the RxD line is pulled low (i.e all 0s) i.e held in spacing state for 1 full character after which Rx Block goes into Idle state. Rx Block gets back to active state when RxD pin is pulled high (i.e all 1s) i.e held in marking state for 1 full character. (Note: Reading U0LSR clears this bit)
  6. Bit 5 – Transmit Holding Register Empty(THRE) : 0 means U0THR contains valid data and 1 means its empty.
  7. Bit 6 – Transmitter Empty (TEMT) : 0 means U0THR and/or U0RSR contains valid data and 1 means that both U0THR and U0RSR are empty.
  8. Bit 7 – Error in RX FIFO(RXFE) : 0 means that U0RBR has no Rx Errors or Rx FIFO is disabled(i.e 0th bit in U0FCR is 0) and 1 means that U0RBR has atleast one error. (Note: This bit is cleared only if U0LSR is read and there are no other subsequent errors in Rx FIFO .. else this bit will stay 1)

4) U0TER – Transmit Enable Register : This register is used to enable UART transmission. When bit-7 (i.e TXEN) is set to 1 Tx block will be enabled and will keep on transmitting data as soon as its ready. If bit-7 is set to 0 then Tx will stop transmission. Other bits are reserved.

Interrupt Related Registers :

1) U0IER – Interrupt Enable Register: Set a bit to 0 to disable and 1 to enable the corresponding interrupt.

  1. Bit 0 – RBR Interrupt Enable
  2. Bit 1 – THRE Interrupt Enable
  3. Bit 2 – RX Line Status Interrupt Enable
  4. Bit 3 – ATBOInt Enable
  5. Bit 4 – ATEOInt Enable

Where ATBOInt = Auto Baud Time-Out Interrupt , ATEO = End of Auto Baud Interrupt and rest of the bits are reserved.

2) U0IIR – Interrupt Identification Register: Refer User Manual when in doubt. In some application the usage of this register might get a bit complicated.

This register is organized as follows:

  1. Bit 0 – Interrupt Pending : 0 means atleast one interrupt is pending , 1 means no interrupts are pending. Note: This bit is ACTIVE LOW!
  2. Bits [3 to 1] – Interrupt Identification : [011] is for Receive Line Status(RLS) , [010] means Receive Data Available(RDA) , 110 is for Character Time-out Indicator(CTI) , [001] is for THRE Interrupt.
  3. Bits [7 to 6] – FIFO Enable.
  4. Bit 8 – ABEOInt : 1 means Auto Baud Interrupt has successfully ended and 0 otherwise.
  5. Bit 9 – ABTOInt : 1 means Auto Baud Interrupt has Timed-out.
  6. All others bits are reserved

CIRCUIT DIAGRAM :

uart

CODE FOR PROJECT :

main.c – 

header.h –

lcd.h –

uart.h –

 

pll.h –

 

COMING SOON ………………….

video