What is ISA ?
Instruction set architecture(ISA) is the set of processor design techniques used to implement the instruction work flow on hardware. In more practical words, ISA tells you that how your processor going to process your program instructions.
There is no standard computer architecture accepting different types like CISC, RISC, etc.
what is CISC ?
A complex instruction set computer (CISC /pronounce as ˈsisk’/) is a computer where single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) or are capable of multi-step operations or addressing modes within single instructions, as its name suggest “COMPLEX INSTRUCTION SET”.
What is RISC ?
A reduced instruction set computer (RISC /pronounce as ˈrisk’/) is a computer which only use simple instructions that can be divide into multiple instructions which perform low-level operation within single clock cycle, as its name suggest “REDUCED INSTRUCTION SET”
Understand RISC & CISC architecture with example
Let we take an example of multiplying two numbers
A = A * B; <<<======this is C statement
The CISC Approach :- The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. This is achieved by building processor hardware that is capable of understanding & executing a series of operations, this is where our CISC architecture introduced .
For this particular task, a CISC processor would come prepared with a specific instruction (we’ll call it “MULT”). When executed, this instruction
- Loads the two values into separate registers
- Multiplies the operands in the execution unit
- And finally third, stores the product in the appropriate register.
Thus, the entire task of multiplying two numbers can be completed with one instruction:
MULT A,B <<<======this is assembly statement
MULT is what is known as a “complex instruction.” It operates directly on the computer’s memory banks and does not require the programmer to explicitly call any loading or storing functions.
- Compiler has to do very little work to translate a high-level language statement into assembly
- Length of the code is relatively short
- Very little RAM is required to store instructions
- The emphasis is put on building complex instructions directly into the hardware.
The RISC Approach :- RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the “MULT” command described above could be divided into three separate commands:
- “LOAD” which moves data from the memory bank to a register
- “PROD” which finds the product of two operands located within the registers
- “STORE” which moves data from a register to the memory banks.
In order to perform the exact series of steps described in the CISC approach, a programmer would need to code four lines of assembly:
LOAD R1, A <<<======this is assembly statement
LOAD R2,B <<<======this is assembly statement
PROD A, B <<<======this is assembly statement
STORE R3, A <<<======this is assembly statement
At first, this may seem like a much less efficient way of completing the operation. Because there are more lines of code, more RAM is needed to store the assembly level instructions. The compiler must also perform more work to convert a high-level language statement into code of this form.
- Each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle “MULT” command.
- These RISC “reduced instructions” require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers. Because all of the instructions execute in a uniform amount of time (i.e. one clock)
- Pipelining is possible.
LOAD/STORE mechanism:- Separating the “LOAD” and “STORE” instructions actually reduces the amount of work that the computer must perform. After a CISC-style “MULT” command is executed, the processor automatically erases the registers. If one of the operands needs to be used for another computation, the processor must re-load the data from the memory bank into a register. In RISC, the operand will remain in the register until another value is loaded in its place.
Comparison of RISC & CISC
Emphasis on hardware
Emphasis on software
reduced instruction only
Memory-to-memory: “LOAD” and “STORE” incorporated in instructions
Register to register: “LOAD” and “STORE” are independent instructions
high cycles per second, Small code sizes
Low cycles per second, large code sizes
Transistors used for storing complex instructions
Spends more transistors on memory registers
Example of RISC & CISC
Examples of CISC instruction set architectures are PDP-11, VAX, Motorola 68k, and your desktop PCs on intel’s x86 architecture based too .
Examples of RISC families include DEC Alpha, AMD 29k, ARC, Atmel AVR, Blackfin, Intel i860 and i960, MIPS, Motorola 88000, PA-RISC, Power (including PowerPC), SuperH, SPARC and ARM too.
Which one is better ?
We can not differentiate RISC and CISC technology because both are suitable at its specific application. What counts is how fast a chip can execute the instructions it is given and how well it runs existing software. Today, both RISC and CISC manufacturers are doing everything to get an edge on the competition.
What’s new ?
You might thinking that RISC is nowdays used in microcontroller application widely so its better for that particular application and CISC at desktop application. But reality is boh are at threat position cause of a new technology called EPIC.
EPIC ( Explicitly Parallel Instruction Computing ) :-EPIC is a invented by Intel and is in a way, a combination of both CISC and RISC. This will in theory allow the processing of Windows-based as well as UNIX-based applications by the same CPU.
Intel is working on it under code-name Merced. Microsoft is already developing their Win64 standard for it. Like the name says, Merced will be a 64-bit chip.
If Intel’s EPIC architecture is successful, it might be the biggest thread for RISC. All of the big CPU manufactures but Sun and Motorola are now selling x86-based products, and some are just waiting for Merced to come out (HP, SGI). Because of the x86 market it is not likely that CISC will die soon, but RISC may.
So the future might bring EPIC processors and more CISC processors, while the RISC processors are becoming extinct.
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